μPILR Flip Chip Interconnect
Tessera’s μPILR Flip Chip is a scalable, copper interconnect technology addressing the industry’s need for ever-finer pitch flip chip solutions with larger die, ultra low-K dielectrics and lead-free materials. The μPILR Flip Chip technology uses existing PCB substrate and assembly infrastructure and materials, to provide a simple solution for flip chip die-attach via integrated copper pillars on the substrate itself. As a result, assembly yield is improved, and cost of adoption and ownership is reduced by minimizing back-end wafer processing needs. Most significantly, the μPILR Flip Chip structure significantly improves product performance and reliability.

Enabling High I/O & Fine Pitch Without Reliability Trade-Offs
μPILR Flip Chip technology has been proven at 130-180μm pitch using 3-4-3 build-up substrates. 80-125μm interconnect pitch is designed for 1-2-1 substrates, and leverages the same copper μPILR structure and processes. For reference, typical design rules for μPILR Flip Chip substrates at 150μm and 125μm pitch are shown in Table 1. The 150μm pitch design is focused on processors for high-performance computing devices. The 80-125μm pitch design is focused on application and baseband processors for smart portable devices. As the pitch shrinks, solder mask imaging rules become limiting, so for very fine pitch designs, solder mask defined pads can be replaced by nonsolder mask pad arrays.

μPILR Substrate Manufacturing and Assembly
The μPILR technology’s copper interconnects are fabricated as an integral part of the PCB substrate. The manufacturing process integrates easily into existing substrate manufacturing lines and utilizes conventional materials and equipment. Package assembly can be accomplished on conventional flip chip assembly lines without any changes to processes or equipment.

Package-Level Reliability
The μPILR Flip Chip BGA reliability test vehicles replicate high-performance logic packages (40-45mm) with large die (18-20mm), complex substrates (3-4-3 build-up), lead-free materials and high I/O interconnect (4000-10000). The low-K temperature cycle test vehicle features a 45x45mm body size, 18x16.7mm die size and 4,133 interconnects at 180μm/360μm bump pitch. The electro-migration test vehicle uses a 40x40mm body size, 20x18mm die size and 10,132 bumps at 150μm/200μm bump pitch.